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max14820 io-link device transceiver 19-5787; rev 6; 3/14 general description the max14820 transceiver is suitable for io-link ? devices and 24v binary sensors/actuators. all specified io-link data rates are supported. in io-link applica - tions, the transceiver acts as the physical layer interface to a microcontroller running the data-link layer protocol. additional 24v digital inputs and outputs are provided. two internal linear regulators generate common sensor and actuator power requirements: 5v and 3.3v. on-board c/q and do drivers are independently config - urable for push-pull, high-side (pnp), or low-side (npn) operation. the device detects the io-link c/q wake-up condition and generates a wake-up signal on the active- low wu output. the c/q and di inputs have selectable current loads for use in actuators.an spi? interface allows configuration and monitoring of the devices. extensive alarm conditions are detected and communicated through the irq output and the spi inter - face. the devices feature reverse-polarity, short-circuit, and thermal protection. all power lines are monitored for undervoltage conditions. the c/q driver is specified for sinking/sourcing 300ma. the do driver is specified for sinking/sourcing 135ma. the device is available in a 4mm x 4mm, 24-pin tqfn package, and is specified over the extended -40 n c to +85 n c temperature range. applications io-link sensors industrial sensors and actuators io-link actuators features s io-link specification v.1.0 and v.1.1 physical layer compliant s supports com1, com2, and com3 data rates s io-link device wake-up detection s push-pull, high-side, or low-side outputs s 300ma specified c/q output drive s 1f c/q and do load-drive capability s auxiliary 24v, 135ma digital output s auxiliary 24v digital input s optional 6ma/7ma current loads at both 24v inputs s 5v and 3.3v linear regulators s reverse-polarity protected 24v supply output s emi emission control through slew-controlled driver s spi interface for configuration and monitoring s 2.5v to 5v logic interface levels s reverse-polarity and short-circuit protection on all 24v inputs/outputs s high-temperature warning and thermal shutdown s extensive fault monitoring and reporting s -40 n c to +85 n c operating temperature range s 4mm x 4mm tqfn package io-link is a registered trademark of profibus user organization (pno).spi is a trademark of motorola, inc. ordering information appears at end of data sheet. typical operating circuit for related parts and recommended products to use with this part, refer to: www.maximintegrated.com/max14820.related evaluation kit available 1 2 4 3 10k max14820 0.8 1f 1f 1f 0.1f v cc uv gpio2 ldoin do spi c/q l+ l- gnd di gnd v p v 5 v cc ldo33 v l txq microcontroller wu irq rx rx txc tx txen rts lo gpio1 3.3v 5v 10 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim integrated?s website at www.maximintegrated.com. downloaded from: http:///
max14820 io-link device transceiver 2 maxim integrated functional diagram max14820 uv monitor uv v cc v 5 ldo33 ldoin status and configuration 3.3v ldo filter driver driver wake-up detect protection 5v ldo v l sdi cs rx li lo c/q protection di do doen gnd c/qload diload sdo sclk irq wu txqtxc txen v p protection protection downloaded from: http:///
max14820 io-link device transceiver 3 maxim integrated (all voltages referenced to gnd, unless otherwise noted.)v cc ......................................................................... -40v to +40v v p (i vp < 50ma) ..... the higher of -0.3v and (v cc - 1v) to +40v ldoin .................................................................... -0.3v to +40v v 5 ..................... -0.3v to the lesser of (v ldoin + 0.3v) and +6v ldo33 ..................... -0.3v to the lesser of (v 5 + 0.3v) and +6v v l ............................................................................. -0.3v to +6v di ........................................................................... -40v to +40v c/q, do ...................... min: the higher of -40v and (v cc - 40v) max: the lesser of +40v and (v cc + 40v) logic inputs txc, txq, txen, lo, cs , sdi, sclk ..... -0.3v to (v l + 0.3v) logic outputs rx, wu , li, sdo, irq ............................. -0.3v to (v l + 0.3v) uv ........................................................................ -0.3v to +6v continuous current into any logic pin ........................... q 50ma continuous power dissipation tqfn (derate 27.8mw/ n c above +70 n c)..................2222mw operating temperature range .......................... -40 n c to +85 n c maximum junction temperature ..................................... +150 n c storage temperature range ............................ -65 n c to +150 n c lead temperature (soldering, 10s) ................................ +300 n c soldering temperature (reflow) ...................................... +260 n c tqfn junction-to-ambient thermal resistance ( b ja ) .......... 36 n c/w junction-to-case thermal resistance ( b jc ) ................. 3 n c/w absolute maximum ratings note 1: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four-layer board. for detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial . stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress ratings only, and functional opera - tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. package thermal characteristics (note 1) dc electrical characteristics (v cc = 18v to 36v, v l = 2.3v to 5.5v, v gnd = 0v; all logic inputs at v l or gnd; t a = -40 n c to +85 n c, unless otherwise noted. typical values are at v cc = 24v, v l = 3.3v, and t a = +25 n c, unless otherwise noted.) (note 2) parameter symbol conditions min typ max units v cc supply voltage v cc for driver operation 9 36 v v cc supply current i cc v cc = 24v, c/q as input, no load on v 5 or ldo33, ldoin not connected to v p , v ldoin = 24v 1 2.5 ma v cc undervoltage lockout threshold v ccuvlo v cc falling 6 7.4 9 v v cc undervoltage lockout threshold hysteresis v ccuvlo_hyst 200 mv v 5 supply current i 5_in ldoin shorted to v 5 , external 5v applied to v 5 , no switching, ldo33 disabled 3 ma v 5 undervoltage lockout threshold v 5uvlo v 5 falling 2.0 v v l logic-level supply voltage v l 2.3 5.5 v v l logic-level supply current i l all logic inputs at v l or gnd 5 f a v l undervoltage threshold v luvlo v l falling 0.65 0.95 1.30 v 5v ldo (v 5 ) ldoin input voltage range v ldoin 7 36 v ldoin supply current i ldoin v ldoin = 24v, c/q is configured as an input, no load on v 5 or ldo33 2.5 5 ma downloaded from: http:///
max14820 io-link device transceiver 4 maxim integrated dc electrical characteristics (continued)(v cc = 18v to 36v, v l = 2.3v to 5.5v, v gnd = 0v; all logic inputs at v l or gnd; t a = -40 n c to +85 n c, unless otherwise noted. typical values are at v cc = 24v, v l = 3.3v, and t a = +25 n c, unless otherwise noted.) (note 2) parameter conditions min typ max units v 5 output voltage range v 5 no load on v 5 , 7v p v ldoin p 36v 4.75 5.00 5.25 v v 5 load regulation 1ma < i load < 10ma, v ldoin = 7v, 0.1 f f bypass capacitor on v 5 0.8 % 1ma < i load < 30ma, v ldoin = 7v, 0.1 f f bypass capacitor on v 5 , 10 w ?1 f f compensation network added to v 5 0.8 3.3v ldo (ldo33)ldo33 output voltage v ldo33 no load on ldo33 3.1 3.3 3.5 v ldo33 undervoltage lockout threshold v ldo33uvlo v ldo33 falling 2.4 v ldo33 load regulation 1ma < i load < 20ma, v ldoin = 7v 0.25 % 24v interfacec/q driver output voltage high v oh_c/q c/q high-side enabled, i c/q = -300ma, 9v p v cc p 36v v cc - 3 v cc - 1.8 v c/q driver output voltage low v ol_c/q c/q low-side enabled, i c/q = +300ma, 9v p v cc p 36v 1.95 3 v c/q driver source current limit i oh_c/q c/q high-side enabled, v c/q < (v cc - 3v), 9v p v cc p 36v +375 +480 ma c/q driver sink current limit i ol_c/q c/q low-side enabled, v c/q > 3v, 9v p v cc p 36v -480 -375 ma do driver output voltage high v oh_do do high-side enabled, i do = +135ma, 9v p v cc p 36v v cc - 3 v cc - 1.75 v do driver output voltage low v ol_do do low-side enabled, i do = -135ma, 9v p v cc p 36v 1.85 3 v do driver source current limit i oh_do do high-side enabled, v do < (v cc - 3v) 200 ma do driver sink current limit i ol_do do high-side enabled, v do > 3v -200 ma c/q, di input voltage range v in for valid rx, li -1.0 v cc + 1.0 v c/q input threshold high v ih_c/q c/q driver disabled 10.5 13 v c/q input threshold low v il_c/q c/q driver disabled 8.0 11.5 v c/q input hysteresis v hys_c/q c/q driver disabled 1.0 v di input threshold high v ih_di 6.8 8 v di input threshold low v il_di 5.2 6.4 v di input hysteresis v hys_di 1 v c/q weak pulldown current i pdc/q c/q driver disabled, v c/q = (v cc - 1v) 100 400 f a downloaded from: http:///
max14820 io-link device transceiver 5 maxim integrated dc electrical characteristics (continued)(v cc = 18v to 36v, v l = 2.3v to 5.5v, v gnd = 0v; all logic inputs at v l or gnd; t a = -40 n c to +85 n c, unless otherwise noted. typical values are at v cc = 24v, v l = 3.3v, and t a = +25 n c, unless otherwise noted.) (note 2) parameter symbol conditions min typ max units do weak pulldown current i pddo do driver disabled, v cc = 36v, v do = (v cc - 1v) 40 120 f a di weak pulldown current i pddi di load disabled, v cc = 36v, v di = (v cc - 1v) 50 300 f a c/q input capacitance c c/q c/q driver disabled 40 pf do input capacitance c do do driver disabled 40 pf di input capacitance c di 20 pf c/q, di current sinkc/q load current i llm_c/q c/q load enabled (c/qload = 1) 0v p v c/q p 5v 0 9 ma 5v p v c/q 5 9 di load current i llm_di di load enabled (diload = 1) 0v p v di p 5v 0 9 ma 9v p v di 6 7.5 9 logic inputs (txc, txq, txen, lo, cs , sdi, sclk) logic-input voltage low v il 0.3 x v l v logic -input voltage high v ih 0.7 x v l v logic-input leakage current i leak logic input = gnd or v l -1 +1 f a logic-input capacitance c in 5 pf logic outputs (rx, wu , li, uv, sdo, irq ) logic-output voltage low v ol i out = -5ma 0.4 v logic-output voltage high v ohrx , v ohwu , v ohli , v ohsdo, v ohirq , i out = 5ma (note 3) v l - 0.6 v sdo leakage current i lk_sdo sdo disabled, sdo = gnd or v l -1 +1 f a thermal shutdown thermal warning threshold die temperature rising, otemp bit is set +115 n c thermal warning threshold hysteresis die temperature falling, otemp bit is cleared 20 n c thermal shutdown threshold die temperature rising +150 n c thermal shutdown hysteresis 20 n c downloaded from: http:///
max14820 io-link device transceiver 6 maxim integrated ac electrical characteristics(v cc = 18v to 36v, v l = 2.3v to 5.5v, v gnd = 0v; all logic inputs at v l or gnd; t a = -40 n c to +85 n c, unless otherwise noted. typical values are at v cc = 24v, v l = 3.3v, and t a = +25 n c, unless otherwise noted.) (note 2) parameter symbol conditions min typ max units c/q, do, di interfacesdata rate dr hislew = 1 4.8 230.4 kbps hislew = 0 4.8 38.4 driver (c/q, do)driver low-to-high propagation delay t pdlh push-pull or high-side (pnp) configuration, figure 1 hislew = 1 0.5 2 f s hislew = 0 1.6 5 driver high-to-low propagation delay t pdhl push-pull or low-side (npn) configuration, figure 1 hislew = 1 0.5 2 f s hislew = 0 1.6 5 driver skew t skew |t pdlh - t pdhl | 0.1 2 f s driver rise time t rise push-pull or high-side (pnp) configuration, figure 1 hislew = 1 0.4 1 f s hislew = 0 1.5 4 driver fall time t fall push-pull or low-side (npn) configuration, figure 1 hislew = 1 0.4 1 f s hislew = 0 1.4 4 driver enable time high t enh push-pull or high-side (pnp) configuration, figure 3 hislew = 1 0.3 1 f s hislew = 0 0.8 7 driver enable time low t enl push-pull or low-side (npn) configuration, figure 2 hislew = 1 0.3 1 f s hislew = 0 0.9 7 driver disable time high t dish push-pull or high-side (pnp) configuration, figure 2 (note 4) hislew = 1 1.6 3 f s hislew = 0 1.6 3 driver disable time low t disl push-pull or low-side (npn) configuration, figure 3 (note 4) hislew = 1 0.1 3 f s hislew = 0 0.1 3 receiver (c/q, di) (figure 4)receiver low-to-high propagation delay t prlh rxfilter = 1 0.2 2 f s rxfilter = 0 0.4 2 receiver high-to-low propagation delay t prhl rxfilter = 1 0.3 2 f s rxfilter = 0 0.5 2 wake-up detection (figure 5)wake-up input minimum pulse width t wumin 30 40 50 f s wake-up input maximum pulse width t wumax 120 140 160 f s wu output low time t wul valid wake-up condition on c/q 120 190 260 f s downloaded from: http:///
max14820 io-link device transceiver 7 maxim integrated ac electrical characteristics (continued)(v cc = 18v to 36v, v l = 2.3v to 5.5v, v gnd = 0v; all logic inputs at v l or gnd; t a = -40 n c to +85 n c, unless otherwise noted. typical values are at v cc = 24v, v l = 3.3v, and t a = +25 n c, unless otherwise noted.) (note 2) note 2: all devices are 100% production tested at t a = +25 n c. limits over the operating temperature range are guaranteed by design. note 3: uv is an open-drain output. connect uv to a voltage less than 5.5v through an external pullup resistor. note 4: disable time measurements are load dependent. parameter symbol conditions min typ max units spi timing ( cs , sclk, sdi, sdo) (figure 6) sclk clock period t ch+cl 83.3 ns sclk pulse-width high t ch 41.65 ns sclk pulse-width low t cl 41.65 ns cs fall to sclk rise time t css 20 ns sclk rise to cs rise hold time t csh 20 ns sdi hold time t dh 10 ns sdi setup time t ds 10 ns output data propagation delay t do 32 ns sdo rise and fall times t ft 20 ns minimum cs pulse t csw 76.8 ns downloaded from: http:///
max14820 io-link device transceiver 8 maxim integrated figure 1. c/q and lo driver propagation delays and rise/fall timesfigure 2. c/q driver enable low and disable high timing with external pullup resistor tx cc /q or do txen (txc and txq) or lo c/q or do t pdhl t fall t rise t pdlh 90% v l v l v cc 0v0v 0v 50% 50% 10% 3.3nf 5k txen gnd txq lo max14820 v l txctxq c/q v cc txen c/q t enl t dish v l v cc 0v0v 10% 10% 3.3nf 5k txen gnd max14820 downloaded from: http:///
max14820 io-link device transceiver 9 maxim integrated figure 3. c/q driver enable high and disable low timingfigure 4. c/q and di receiver propagation delays c/q 3.3nf 5k txen gnd txctxq txen c/q t enh t disl v l v cc 0v0v 90% 90% max14820 rx or li c/q or di rx or li t prlh t prhl v cc v l 0v0v 50% 50% 15pf gnd txen max14820 c/q or di downloaded from: http:///
max14820 io-link device transceiver 10 maxim integrated figure 5. wake-up detection timingfigure 6. spi timing diagram txen txc and txq note: the max14820 recognizes a wake-up pulse when c/q is shorted from high-to-low or from low-to-high for t wumin < t wu < t wumax . c/q t wumin < t wu < t wumax t wul < t wumin no wake-up txc and txq txen gnd c/q wu wu max14820 t csh t cl t css t ch t csh cs sclk sdi sdo t ds t dh t do downloaded from: http:///
max14820 io-link device transceiver 11 maxim integrated typical operating characteristics (v cc = 24v, ldoin = v p , v l = ldo33, c/q and do in push-pull configuration, t a = +25 n c, unless otherwise noted.) c/q driver-output high vs. load current max14820 toc01 load current (ma) v oh_c/q (v) 350 300 250 200 150 100 50 19 20 21 22 23 24 2518 0 400 t a = +25c t a = +85c t a = -40c txen = v l txc = txq = gnd c/q driver-output low vs. sink current max14820 toc02 sink current (ma) v ol_c/q (v) 350 300 250 200 150 100 50 1 2 3 4 5 6 70 0 400 t a = +25c t a = +85c t a = -40c txen = v l txc = txq = v l do driver-output high vs. load current max14820 toc03 load current (ma) v oh_do (v) 200 150 100 50 20 21 22 23 24 2519 0 250 t a = +25c t a = +85c t a = -40c do driver is enabledlo = gnd do driver-output low vs. sink current max14820 toc04 sink current (ma) v ol_do (v) 200 150 100 50 1 2 3 4 5 6 70 0 250 t a = +25c t a = +85c t a = -40c do driver is enabledlo = v l c/q driver propagation delay vs. temperature (hislew = 0) max14820 toc05 temperature (c) t pdhl (s) 75 60 30 45 -15 0 15 -30 1.12 1.14 1.16 1.18 1.20 1.22 1.24 1.26 1.28 1.301.10 -45 90 txen = v l txc = txq c/q driver propagation delay vs. temperature (hislew = 1) max14820 toc06 temperature (c) t pdhl (s) 75 60 -30 -15 0 30 15 45 0.39 0.40 0.41 0.42 0.43 0.44 0.45 0.460.38 -45 90 txen = v l txc = txq downloaded from: http:///
max14820 io-link device transceiver 12 maxim integrated typical operating characteristics (continued) (v cc = 24v, ldoin = v p , v l = ldo33, c/q and do in push-pull configuration, t a = +25 n c, unless otherwise noted.) c/q driver output switching (hislew = 0) max14820 toc07 2s/div v c/q 5v/div v txc=txq 2v/div 0v0v ch1 ch2 1.430s ch1 ch2 1.330sch2 rise 1.583s ch2 fall 1.455s c/q driver output switching (hislew = 1) max14820 toc08 2s/div v c/q 5v/div v txc=txq 2v/div 0v0v ch1 ch2 357.1ns ch1 ch2 335.4nsch2 rise 343.5ns ch2 fall 331.7ns receiver propagation delay vs. temperature (rxfilter = 0) max14820 toc09 temperature (c) t prhl (ns) 75 60 30 45 -15 0 15 -30 150 200 250 300 350 400 450 500 550100 -45 90 di to li c/q to rx receiver propagation delay vs. temperature (rxfilter = 1) max14820 toc10 temperature (c) t prhl (ns) 75 60 -30 -15 0 30 15 45 50 100 150 200 250 300 350 400 0 -45 90 di to li c/q to rx wake-up detection max14820 toc11 40s/div v c/q 10v/div0v 0v v wu 2v/div c/q short-circuit protection max14820 toc12 40s/div i source 200ma/div txen = v l , txc = txq = gnd t short = 200s v c/q 10v/div0v 0ma 0v v irq 2v/div downloaded from: http:///
max14820 io-link device transceiver 13 maxim integrated typical operating characteristics (continued) (v cc = 24v, ldoin = v p , v l = ldo33, c/q and do in push-pull configuration, t a = +25 n c, unless otherwise noted.) c/q short-circuit protection max14820 toc13 40s/div i sink 200ma/div txen = v l , txc = txq = gnd t short = 200s v c/q 10v/div0v 0ma 0v v irq 2v/div v cc supply current vs. c/q data rate max14820 toc17 c/q data rate (kbps) icc (ma) 100 10 2 4 6 8 10 12 14 16 18 0 1 1000 vldoin = v5 = 5vtxen = vl hislew = 1 v cc = 36v v cc = 30v v cc = 24v v 5 load regulation max14820 toc14 load current (ma) % voltage change 40 30 20 10 -0.45 -0.40 -0.35 -0.30 -0.25 -0.20 -0.15 -0.10 -0.05 0 -0.50 05 0 t a = +25c t a = +85c t a = -40c ldoin supply current vs. ldoin voltage max14820 toc18 v ldoin (v) i ldoin (ma) 33 30 12 15 18 24 21 27 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0 93 6 t a = +25c t a = +85c t a = -40c v cc = 36v c/q and do drivers enabledldo5, ldo33 are loaded txc = txq = lo = v l ldo33 load regulation max14820 toc15 load current (ma) % voltage change 40 45 35 30 25 20 15 5 10 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0 -0.7 05 0 t a = +25c t a = +85c t a = -40c v cc supply current vs. v cc voltage max14820 toc16 v cc voltage (v) i cc (ma) 33 30 24 27 15 18 21 12 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 0 93 6 t a = +25c t a = +85c t a = -40c v ldoin = 7v c/q and do drivers enabledldo5, vp unloaded c/q and di current loads off txc = txq = lo = v l downloaded from: http:///
max14820 io-link device transceiver 14 maxim integrated pin configuration pin description pin name function 1 ldoin 5v linear regulator input. bypass ldoin to gnd with a 0.1 f f ceramic capacitor. 2 v 5 5v power-supply input and 5v linear regulator output. bypass v 5 to gnd with a 0.1 f f ceramic capacitor for 10ma load capability. add the recommended compensation network to increase the source capability to 30ma. see the 5v and 3.3v linear regulators section for more information. 3 ldo33 3.3v linear regulator output. bypass ldo33 to gnd with a 1 f f ceramic capacitor. 4 irq active-low interrupt request output. irq is a push-pull output referenced to v l . 5 sclk spi clock input 6 cs active-low spi chip-select input 7 sdo spi serial-data output 8 sdi spi serial-data input 9 v l logic-level supply input. v l defines the logic levels on all the logic inputs and outputs. bypass v l to gnd with a 0.1 f f ceramic capacitor. 10 i.c. internally connected. connect to v l or leave unconnected. it is recommended to connect to v l . 11 txq transmit level input. the logic on the c/q output is the inverse logic level of the signals on the txc and txq inputs. txq is anded with txc. drive txq high if not in use. 12 txc transmit communication input. the logic on the c/q output is the inverse logic level of the signals on the txc and txq inputs. txc is anded with txq. drive txc high if not in use. 13 txen transmitter enable. drive txen high to enable the c/q transmitter. txen is referenced to v l . 2324 22 21 87 9 v 5 irq sclk cs 10 ldoin liwu rx uvtxen 12 do 45 6 17 18 16 14 13 v cc v p i.c.v l sdisdo *ep *connect exposed pad to gnd. ldo33 lo 3 15 c/q 20 11 txq gnd 19 12 txc di tqfn (4mm 4mm) top view + max14820 downloaded from: http:///
max14820 io-link device transceiver 15 maxim integrated pin description (continued) pin name function 14 rx receiver output. rx is the inverse logic level of c/q. rx is always high when the rxdis bit in the cqconfig register is set to 1. 15 wu active-low wake-up output. wu is a push-pull output referenced to v l . wu pulses low for 190 f s (typ) when a valid wake-up pulse is detected on the c/q line. 16 lo logic input of the do output. lo is the logic input that drives do. lo is referenced to v l . 17 li logic output of the 24v di logic input. li is the inverse logic of di. li is referenced to v l . 18 uv open-drain undervoltage indicator output. in case of an undervoltage, the uv open-drain transistor is off. 19 di 24v logic-level digital input 20 gnd ground 21 c/q sio/io-link data input/output. drive txen high to enable the c/q driver. the logic on the c/q output is the inverse logic level of the signals on the txc and txq inputs. rx is the logic inverse of c/q. the c/q driver output level can be set by the txc/txq inputs or programmed by the q bit. the level on c/q can be read by the rx ouput or the q lvl bit. 22 do 24v logic-level digital output. do is the inverse logic level of the lo input and can be digitally controlled through the dioconfig register. 23 v cc power-supply input. bypass v cc to gnd with a 1 f f ceramic capacitor. 24 v p protected 24v supply output. v p is one diode drop below v cc . v p is reverse-polarity protected and can be used as a 24v protected supply to the sensor or actuator electronics. ? ep exposed pad. connect ep to gnd. downloaded from: http:///
max14820 io-link device transceiver 16 maxim integrated detailed description the max14820 is a sensor/actuator transceiver designed for io-link ? device applications supporting all the specified io-link data rates. in io-link applications, the devices act as the physical layer interface to a microcon - troller running the data-link layer protocol. the device contains an additional 24v digital input and an additional 24v digital output. two internal linear regulators gener - ate common sensor and actuator power requirements: 5v and 3.3v. the device detects io-link wake-up conditions on the c/q line and generates a wake-up signal on the wu output. the c/q and do drivers are independently configurable to any one of three driver output types: push-pull, high-side (pnp), or low-side (npn). the c/q and di inputs have selectable current sinks that can be enabled for use in actuators where the master requires a type 2 load. these devices are configured and monitored through an spi ? interface. extensive alarms are available through spi. 24v interface the device features an io-transceiver interface capable of operating with voltages up to 36v. this is the 24v inter - face and includes the c/q input/output, the logic-level digital output (do), and the logic-level digital input (di). configurable drivers the device features selectable push-pull, high-side (pnp), or low-side (npn) switching drivers at c/q and do. set the c/q_n/p and c/q_pp bits in the cqconfig reg - ister to select the driver mode for the c/q driver. when configured as a push-pull output, c/q switches between v p and ground. set the c/q_pp bit to 1 to select push- pull operation at c/q. set the c/q_pp bit to 0 to configure the c/q output for open-drain operation. the c/q_n/p bit selects npn or pnp operation when c/q is configured as an open-drain output. set the don/p and dopp bits in the dioconfig register to select the driver mode for the do output. when con - figured as a push-pull output, do switches between v cc and ground. set the dopp bit to 1 for push-pull operation. the don/p bit selects npn or pnp operation when do is configured as an open-drain output. set the dopp bit to 0 to select high-side or low-side operation at do. c/q driver and receiver the txen input enables the c/q driver. drive txen high to enable the c/q driver. drive txen low to disable the driver. the device?s c/q driver is specified for 300ma to drive large capacitive loads of up to 1 f f and dynamic imped - ances like incandescent lamps. the maximum load cur - rent for c/q is limited to 480ma.the hislew bit increases the slew rate of the c/q and do driver outputs. set hislew to 1 for data rates of 230kbps or higher. set hislew to 0 to reduce both the c/q and do driver slew rates to reduce emi emission and reflections. the c/q receiver is always on. disable the rx output through the rxdis bit in the cqconfig register. set the rxdis bit to 1 to set the rx output high. set the rxdis bit to 0 for normal receive operation. the c/q receiver has an analog lowpass filter to reduce high-frequency noise present on the line. set the rxfilter bit in the cqconfig register to 0 to set the filter corner frequency to 500khz (typ). set the rxfilter bit to 1 to set the corner frequency of the filter to 1mhz (typ). noise filters are present on both the c/q and di receivers and are controlled simultaneously by the rxfilter bit. c/q fault detection the device registers a c/qfault condition under either of two conditions: 1) when it detects a short circuit for longer than 140s (typ). a short condition exists when the c/q driver?s load current exceeds the 375ma (typ) current limit. 2) when it detects a voltage level error at the c/q out - put. a voltage level error occurs when the c/q driver is configured for open-drain operation (npn or pnp), the driver is turned off, and the c/q voltage is not pulled to exceed the c/q receiver?s threshold levels (< 8v or > 13v) by the external supply. when a c/qfault error occurs, the c/qfault and c/qfaultint bits are set, irq asserts, and the driver is turned off 240s (typ) after the start of the fault condition.when a short-circuit event occurs on c/q, the driver enters autoretry mode. in autoretry mode the device periodically checks whether the short is still present and attempts to correct the driver output. autoretry attempts last for 240s (typ) and occur every 26ms (typ). io-link is a registered trademark of profibus user organization (pno).spi is a trademark of motorola, inc. downloaded from: http:///
max14820 io-link device transceiver 17 maxim integrated do fault detection the device registers a dofault event when a short circuit is present at the do output for 440s. a short condition exists when the load current on the do driver exceeds the 200ma (typ) do current limit. when a short-circuit condition is detected, the do driver enters autoretry mode. in autoretry mode the device periodically checks whether the error is still present. autoretry attempts last for 440s (typ) and occur every 26ms (typ). when a dofault error is detected, the dofault and dofaultint bits are set, irq asserts, and the driver is turned off 440s (typ) after the start of the do faults. reverse-polarity protection the device is protected against reverse-polarity connec - tions on v cc , c/q, do, di, and gnd. any combination of these pins can be connected to dc voltages up to 40v (max). a short to 40v results in a current flow of less than 500 f a. ensure that the maximum voltage between any of these pins does not exceed 40v. 5v and 3.3v linear regulators the device includes two internal regulators to generate 5v (v 5 ) and 3.3v (ldo33). ldo5 is specified for 10ma total external load current (i.e., ldo33 + v5) when bypassed with a 0.1f capacitor to ground. add the compensation network shown in figure 7 to draw up to 30ma of total external load current from the 5v ldo. ldo33 is speci - fied at 20ma. the input of v 5 , ldoin, can be powered from v p , the protected 24v supply output, or to another voltage in the 7v to 36v range.if the external circuits that are powered by the linear reg - ulators require an input bypass capacitance larger than 100nf for 5v or 1f for 3.3v, a compensation network must be added on v5 and/or ldo33. the compensation network consists of a 10 w series resistor and a capaci - tor equal to the value required by the external circuit, as shown in figure 14 . the capacitors c33* and c5* in figure 14 represent the capacitance required by the external circuits. figure 14 does not show any protection diodes for simplicity.when the internal 5v ldo is not used, v5 becomes the supply input for the internal analog and digital func - tions and thus has to be supplied externally so that the max14820 operates normally. the 5v ldo can be disabled by connecting ldoin to v 5 . apply an external voltage of 4.75v to 5.25v to v 5 when the ldo is disabled. use the ldo33dis bit in the mode register to disable ldo33. see the mode register [r1, r0] = [1,1] section for more information. v 5 and ldo33 are not protected against short circuits. power-up the c/q and do driver outputs and the uv output are high impedance when v cc , v 5 , v l , and/or ldo33 volt - ages are below their respective undervoltage thresh - olds during power-up. uv goes low and the drivers are enabled when all these voltages exceed their respective undervoltage lockout thresholds. the drivers are automatically disabled if v cc , v 5 , or v l falls below its threshold. undervoltage detection the device monitors v cc , v 5 , v l , and optionally ldo33 for undervoltage conditions. uv is high impedance when any monitored voltage falls below its uvlo threshold. v cc , v 5 , and v l undervoltage detection cannot be dis - abled. when v cc falls below the v ccuvlo threshold, the uv24 and uv24int bits are set, uv asserts high, and irq asserts low. the spi register contents are unchanged while v 5 is pres - ent, regardless of the state of v cc and ldo33. the spi interface is not accessible and irq is not available when uv is asserted due to a v 5 or v l undervoltage event. when the internal 3.3v ldo regulator voltage (v ldo33 ) falls below the ldo33 undervoltage lockout threshold, the uv33int bit in the status register is set and irq asserts. uv asserts if the uv33en bit in the mode register is set to 1. the uv output deasserts once the undervoltage condi - tion is removed; however, bits in the status register and the irq output are not cleared until the status register has been read. figure 7. v 5 compensation network max14836 10 0.1 f 1 f 1 f v 5 v l 5v ldo33 3.3v downloaded from: http:///
max14820 io-link device transceiver 18 maxim integrated wake-up detection the device detects an io-link wake-up condition on the c/q line in push-pull, high-side (pnp), or low-side (npn) operation modes. a wake-up condition is detected when the c/q output is shorted for 80 f s (typ). wu pulses low for 190 f s (typ) when the device detects a wake-up pulse on c/q ( figure 5 ). set the wuinten bit in the mode register to set the wuint bit in the status register and generate an interrupt on irq when a wake-up pulse is detected. wuint is set and irq asserts immediately after c/q is released when wuinten = 1. thermal protection and considerations the internal ldos and drivers can generate more power than the package for the devices can safely dissipate. ensure that the driver ldo loading is less than the pack - age can dissipate. total power dissipation for the device is calculated using the following equation: p total = p c/q + p do + p 5 + p ldo33 + p q + p clcq + p cldi where p c/q is the power generated in the c/q driver, p do is the power dissipated by the do driver, p 5 and p ldo33 are the power generated by the ldos, p q is the quiescent power generated by the devices, and p clcq and p cldi are the power generated in the c/q and di current sinks.ensure that the total power dissipation is less than the limits listed in the absolute maximum ratings section. use the following to calculate the power dissipation (in mw) due to the c/q driver: p c/q = [i c/q (max)] [0.5 + 7 i c/q (max)] calculate the internal power dissipation of the do driver using the following equation: p do = [i do (max)] [0.5 + 7 i do (max)] calculate the power dissipation in the 5v ldo, v 5 , using the following equation: p 5 = (v ldoin - v 5 ) i 5 where i 5 includes the i ldo33 current sourced from ldo33. calculate the power dissipated in the 3.3v ldo, ldo33, using the following equation: p ldo33 = 1.7v i ldo33 calculate the quiescent power dissipation in the device using the following equation: p q = i cc (max) v cc (max) if the current sinks are enabled, calculate their associ - ated power dissipation as: p clcq = i llm_c/q (max) v c/q (max) p cldi = i llm_di (max) v di (max) overtemperature warning bits in the status and mode registers are set when the temperature of the device exceeds +115 n c (typ). the otempint bit in the status register is set and irq asserts when the otemp bit in the mode register is set. read the status register to clear the otempint bit and irq . the otemp bit is cleared when the die temperature falls to +95 n c. the device continues to operate normally unless the die temperature reaches the +150 n c thermal shutdown threshold, when the device enters thermal shutdown. thermal shutdown all regulators and the c/q and do output drivers are automatically switched off when the internal die tempera - ture exceeds the +150 n c (typ) thermal shutdown thresh - old. spi communication is not available during a thermal shutdown event. regulators are automatically switched on when the inter - nal die temperature falls below the thermal shutdown threshold plus hysteresis. the internal registers return to their default state when the v 5 regulator is switched on. downloaded from: http:///
max14820 io-link device transceiver 19 maxim integrated status register [r1, r0] = [0,0] register functionality the devices have four 8-bit-wide registers for configuration and monitoring ( table 1 ). table 1. register summaryr1/r0 = register address. register r1 r0 d7 d6 d5 d4 d3 d2 d1 d0 status 0 0 wuint dofaultint dilvl q lvl c/qfaultint uv33int uv24int otempint cqconfig 0 1 rxfilter hislew c/q_n/p c/q_pp c/qden q rxdis c/qload dioconfig 1 0 doinv doav don/p dopp doen dobit lidis diload mode 1 1 rst wuinten dofault c/qfault uv24 otemp uv33en ldo33dis bit d7 d6 d5 d4 d3 d2 d1 d0 bit name wuint dofaultint dilvl q lvl c/qfaultint uv33int uv24int otempint read/write r r r r r r r r por state 0 0 x x 0 0 0 0 reset upon read yes yes no no yes yes yes yes x = unknown. these bits are dependent on the di logic and c/q inputs. the status register reflects the logic levels of c/q and di and shows the source of interrupts that cause an irq hardware inter - rupt. the irq interrupt is asserted when an alarm condition (otemp, uv33int, uv24, c/qfault, dofault, wuint) is detected. all bits in the status register are read-only. the interrupt bits return to the default state after the status register is read. if a c/q or do fault condition persists, the associated interrupt bits are immediately set after the status register is read. bit name description d7 wulnt wake-up interrupt request. wuint is set when an io-link wake-up request pulse is detected on c/q and the wuinten bit in the mode register is set. irq asserts when wuint is set to 1. read the status register to clear the wuint bit and deassert irq . d6 dofaultint do fault interrupt. dofaultint interrupt bit and dofault bit (in the mode register) are set when a fault condition occurs on the do driver output. the device registers a fault condition when a short circuit or voltage fault is detected on do (see the do fault detection section for more information). irq asserts when dofaultint is 1. read the status register to clear the dofaultint bit and deassert irq . d5 dilvl di logic level. the dilvl bit mirrors the current logic level at the di input. it is the inverse of the li output and is always active regardless of the state of the lidis bit (table 2). dilvl does not affect irq . dilvl is not changed when the status register is read. downloaded from: http:///
max14820 io-link device transceiver 20 maxim integrated table 2. dilvl and li output table 3. q lvl and rx output v di (v) dilvl bit li output < 5.2 0 high > 8 1 low v c/q (v) q lvl bit rx output < 8 1 high >13 0 low bit name description d4 q lvl c/q logic level. the q lvl bit is the inverse of the logic level at c/q. q lvl is 1 when the c/q input level is low (< 8v) and is 0 when the c/q logic level is high (> 13v) (table 3). q lvl remains active when the c/q receiver is disabled (rxdis = 1). q lvl does not affect irq . q lvl is not changed when the status register is read. d3 c/qfaultint c/q fault interrupt. the c/qfaultint interrupt bit and c/qfault bit (in the mode register) are set when a short circuit or voltage fault occurs on the c/q driver output (see the c/q fault detection section for more information). irq asserts when c/qfault is 1. read the status register to clear the c/qfaultint bit and deassert irq . d2 uv33int internal 3.3v ldo (ldo33) undervoltage warning. both the uv33int interrupt bit and the uv33en bit (in the mode register) are set when v ldo33 falls below the 2.4v ldo33 undervoltage threshold. if uv33en is set in the mode register, irq asserts low when the uv33int bit is 1. read the status register to clear the uv33int bit and deassert irq . set the uv33en bit to 1 in the mode register to enable undervoltage monitoring for uv33int. when enabled, uv asserts high when the uv33int bit is 1. uv deasserts when v ldo33 rises above the ldo33 undervoltage threshold. d1 uv24int v cc undervoltage interrupt. the uv24int interrupt bit and the uv24 bit (in the mode register) are set when the v cc voltage falls below the 7.4v undervoltage threshold. irq asserts low when the uv24int bit is 1. read the status register to clear the uv24int bit and deassert irq . v cc undervoltage detection cannot be disabled. d0 otempint overtemperature warning. the otempint interrupt bit and the otemp bit (in the mode register) are set when a high-temperature condition is detected by the devices. otemp is set when the temperature of the die exceeds +115 n c (typ). otempint is set and irq asserts when the otemp bit is 1. the otempint bit is cleared and irq deasserts when the status register is read. once cleared, otempint is not reset if the die temperature remains above the thermal warning threshold and does not fall below +95 c. downloaded from: http:///
max14820 io-link device transceiver 21 maxim integrated cqconfig register [r1, r0] = [0,1] bit d7 d6 d5 d4 d3 d2 d1 d0 bit name rxfilter hislew c/q_n/p c/q_pp c/qden q rxdis c/qload read/write r/w r/w r/w r/w r/w r/w r/w r/w por state 0 0 0 0 0 0 0 0 use the cqconfig register to control the c/q receiver and driver parameters. all bits in the cqconfig register are read-write and are set to 0 at power-up. bit name description d7 rxfilter c/q and di receiver filter control. the c/q and di receivers have analog lowpass filters to reduce high-frequency noise on the receiver inputs. set the rxfilter bit to 0 to set the filter corner frequency to 500khz. set the rxfilter bit to 1 to set the filter corner frequency to 1mhz (this setting is used for high- speed com3 operation). noise filters on c/q and di are controlled simultaneously by the rxfilter bit. d6 hislew slew-rate control. the hislew bit increases the slew rate for the c/q and do drivers and is used for high-speed com3 (230kbps) data rates. set hislew to 0 for com1 and com2 operation. d5 c/q_n/p c/q driver npn/pnp mode. the c/q_n/p bit selects between low-side (npn) and high-side (pnp) modes when the c/q driver is configured as an open-drain output (c/q_pp = 0). set c/q_n/p to 1 to configure the driver for low-side (npn) operation. set c/q_n/p to 0 for high-side (pnp) operation. d4 c/q_pp c/q driver push-pull operation. set c/q_pp to 1 to enable push-pull operation on the c/q driver. the c/q output is open-drain when c/q_pp is 0. d3 c/qden c/q driver enable/disable. set the c/qden bit to 1 to enable the c/q driver. set c/qden to 0 for hardware (txen) control. see table 4. d2 q c/q driver output logic. the q bit can be used to program the c/q output driver through software. the c/q driver must be enabled and txc = txq must be high to control the c/q driver through the q bit (figure 8). c/q has the same logic polarity as the q bit. set the q bit to 0 to control the c/q driver with txc and txq. the c/q driver output state depends on the c/q_pp and c/q_n/p bits as shown in table 5. note that table 5 assumes that the c/q driver is enabled (txen = v l or c/qden = 1). d1 rxdis c/q receiver enable/disable. set the rxdis bit to 1 to disable the c/q receiver. the rx output is high when rxdis is 1. d0 c/qload c/q current sink enable. set the c/qload bit to 1 to enable the internal current sink at c/q. downloaded from: http:///
max14820 io-link device transceiver 22 maxim integrated table 5. c/q driver output state table 4. c/qden and txen c/q driver control x = don?t care. note: txc and txq = v l . x = don?t care. figure 8. equivalent c/q logic c/qden txen c/q driver 0 low disabled x high enabled 1 x enabled txc and txq (see note) q c/q_pp c/q_n/p c/q configuration c/q state high 1 0 0 pnp, open drain on, c/q is high high 0 0 0 pnp, open drain off, c/q is high impedance high 1 0 1 npn, open drain off, c/q is high impedance high 0 0 1 npn, open drain on, c/q is low high 1 1 x push-pull high high 0 1 x push-pull low txq c/q txc q downloaded from: http:///
max14820 io-link device transceiver 23 maxim integrated dioconfig register [r1, r0] = [1,0] bit d7 d6 d5 d4 d3 d2 d1 d0 bit name doinv doav don/p dopp doen dobit lidis diload read/write r/w r/w r/w r/w r/w r/w r/w r/w por state 0 0 0 0 0 0 0 0 use the dioconfig register to control the di and do interfaces. all bits in the dioconfig register are read-write and are set to 0 at power-up. bit name description d7 doinv do output polarity. set the doinv bit to 1 to invert the logic of the do output. this bit also works in conjunction with the doav (table 6). do tracks the txc and txq inputs with the opposite polarity when both the doav and doinv bits are set. d6 doav do antivalent operation. set the doav bit to 1 to enable antivalent output operation on do. do tracks the txc and txq inputs (and the q bit) when doav is 1 (table 6). the lo input and the dobit are ignored when the doav bit is 1. d5 don/p do driver npn/pnp operation. the don/p bit selects between low- side (npn) and high-side (pnp) modes when the do driver is configured as an open-drain output (dopp = 0). set don/p to 1 to configure the driver for low-side (npn) operation. set don/p to 0 for high-side (pnp) operation. d4 dopp do driver push-pull operation. set the dopp bit to 1 to configure the do driver output for push-pull operation. do is an open-drain output when dopp is 0. d3 doen do driver enable/disable. set the doen bit to 1 to enable the do driver. the do driver is high impedance with a weak pulldown when doen is 0. d2 dobit do driver output logic. the dobit bit can be used to program the do output driver through software. drive lo high to activate dobit programming (figure 9). the do output state is given in table 7. note that table 7 assumes that the doinv bit is 0. d1 lidis li output enable/disable. set the lidis bit to 1 to disable the li output. the li output is low when lidis is 1. d0 diload di current sink enable. set the diload bit to 1 to enable the internal current sink at the di input. downloaded from: http:///
max14820 io-link device transceiver 24 maxim integrated table 6. doav and doinv operationnote 1: low is when v txc , v txq , or v lo = 0v; high is when v txc , v txq , or v lo = v l . note 2: low is when c/q or do < 8v; high is when c/q or do >13v. table 7. do output programmed by dobitx = don?t care. figure 9. equivalent do logic doav doinv txc and txq (note 1) lo (note 1) do (note 2) c/q (note 2) 0 0 low low high high 0 0 low high low high 0 0 high low high low 0 0 high high low low 0 1 low low low high 0 1 low high high high 0 1 high low low low 0 1 high high high low 1 0 low low low high 1 0 low high low high 1 0 high low high low 1 0 high high high low 1 1 low low high high 1 1 low high high high 1 1 high low low low 1 1 high high low low lo dobit dopp don/p do configuration do state high 0 1 x push-pull low high 1 1 x push-pull high high 0 0 0 pnp off, do is high impedance high 1 0 0 pnp on, do is high high 0 0 1 npn on, do is low high 1 0 1 npn off, do is high impedance low x x x see table 6 see table 6 lo dobit do doinv downloaded from: http:///
max14820 io-link device transceiver 25 maxim integrated mode register [r1, r0] = [1,1] bit d7 d6 d5 d4 d3 d2 d1 d0 bit name rst wuinten dofault c/qfault uv24 otemp uv33en ldo33dis read/write r/w r/w r r r r r r/w por state 0 0 0 0 0 0 0 0 use the mode register to reset the max14820 and manage the 3.3v ldo. the mode register has bits that represent the current status of fault conditions. when writing to the mode register, the contents of the fault indication bits (bits 2 to 5) do not change. bit name description d7 rst register reset. set rst to 1 to reset all registers to their default power-up state. then set rst to 0 for normal operation.the status register is cleared and irq deasserts (if asserted) when rst = 1. interrupts are not generated while rst = 1. d6 wuinten wake-up interrupt enable. set wuinten to 1 to enable wake-up interrupt generation. when wuinten is set, the wuint bit in the status register is set and irq asserts when a valid wake-up condition is detected. the c/q driver must be enabled for wake-up detection. the state of wuinten does not affect the wu output. see the wake-up detection section for more information. d5 dofault do fault status. the dofault bit is set when a short circuit or voltage fault occurs at the do driver output (see the do fault detection section for more information). the dofault and dofaultint bits are both set when a fault occurs on do. dofault is cleared when the fault is removed. d4 c/qfault c/q fault status. the c/qfault bit is set when a short circuit or voltage fault occurs at the c/q driver output (see the c/q fault detection section for more information). the c/qfault and c/qfaultint bits are both set when a fault occurs on c/q. c/qfault is cleared when the fault is removed. d3 uv24 v cc undervoltage condition. both the uv24 and the uv24int bits are set when v cc falls below v ccuvlo . uv24 is cleared when v cc rises above the v cc threshold. v 5 must be present for v cc undervoltage monitoring. d2 otemp temperature warning. the otemp bit is set when a high-temperature condition occurs on the devices. both the otempint interrupt in the status register and the otemp bit are set when the junction temperature of the die rises to above +115 n c (typ). the otemp bit is cleared when the junction temperature falls below +95 n c (typ). d1 uv33en ldo33 uv enable. set the uv33en bit to 1 to assert the uv output when ldo33 voltage falls below the 2.4v (typ) undervoltage lockout threshold. the uv33en bit does not affect the uv33int bit in the status register; irq asserts when v ldo33 falls below v ldo33uvlo regardless of the state of uv33en. d0 ldo33dis ldo33 enable/disable. set ldo33dis to 1 to disable the 3.3v linear regulator (ldo33). downloaded from: http:///
max14820 io-link device transceiver 26 maxim integrated spi interface the device communicates through an spi-compatible 4-wire serial interface. the interface has three inputs? clock (sclk), chip select ( cs ), and data in (sdi)?and one output, data out (sdo). the maximum spi clock rate for the device is 12mhz. the spi interface complies with clock polarity cpol = 0 and clock phase cpha = 0 (see figure 10 and figure 11 ). the spi interface is not available when v 5 or v l are not present. figure 10. spi write cycle figure 11. spi read cycle r0 d7 d6 d5 d4 d3 d2 d1 d0 sclk r_ = register addressd_ = data bit = clock edge that initiates latching of sdi data sdi w 00000 r1 cs cs sclk sdi 00 00 0r 1r 0 r d7 d6 d5 d4 d3 d2 d1 d0 sdo x x r_ = register addressd_ = data bit = clock edge that initiates latching of sdi data = clock edge that initiates writing of sdo data downloaded from: http:///
max14820 io-link device transceiver 27 maxim integrated applications information uart interfacing the logic levels of the microcontroller interface i/os (txc, txq, txen, and rx) are defined by v l . the device can be interfaced to microcontrollers where the on-board uart tx output cannot be programmed as a logic output (gpo). in this case, connect the tx output of the uart to the txc input for io-link communication and connect a separate gpo output on the microcontroller to txq for stan - dard io (sio) mode operation ( figure 12 ). as the txq and txc inputs are internally logically anded, the unused input (txc or txq) must be held high while the other is in operation. transient protection inductive load switching, surges, and bursts create high transient voltages. c/q, do, and di should be protect - ed against high overvoltage and undervoltage transients. positive voltage transients on c/q, do, and di must be lim - ited to +55v relative to gnd and negative voltage transients must be limited to -55v (relative to v cc ) on do and c/q and to -55v (relative to gnd) on di. figure 12 shows suitable protection using tvs diodes to meet both the iec 61000- 4-2 esd and iec 61000-4-5 surge testing. other protection schemes may also be suitable. the device has to be protected against transients that occur during hot-plugging of the l+ sensor supply (vcc input). this is achieved by placing a 10 w resistor with 1f capacitor before ldoin and connecting an rc between the sensor supply input and the vcc pin, as shown in figure 13 . the rc time constant of the filter on vcc should be larger or equal to 0.8s. in case that vl is supplied by v5 and the bypass capacitor on v5 is 100nf, the 10 w resistor in series with ldoin is not needed. external powering the max14820 is powered by v cc and v 5 . v l is a reference voltage input to set the logic levels of the microcontroller interface. the logic and spi interface are operational when v 5 and v l are present even if v cc is not present. the v p output provides a reverse-polarity-protected voltage one diode drop below v cc and can be used for supplying external circuitry, like power supplies. the current drawn from v p cannot exceed 50ma. be aware that capacitance on v p can cause transient currents at power-up equal to c x dv cc / dt. in order to reduce power dissipated in the device, an reverse protection diode can be used to power the external circuitry, instead of using vp, as shown in figure 15 . v 5 is typically powered by the internal 5v regulator, but can alternatively be powered by an external 5v regula - tor. when powering v 5 externally, connect ldoin to v 5 . ( figure 15 ). this configuration disables operation of the internal 5v regulator and reduces power consumption. when an external 5v regulator is used to power v5, the v5 bypass capacitance is determined by that regulator, and is not limited to 100nf. figure 12. uart interfacefigure 13. max14820 operating circuit with tvs protection microcontroller txq gpo txc tx txen rts rx rx max14820 max14820 0.8 1f 1f v cc ldoin do 1/2sdc36c 1/2sdc36c gnd c/q 1/2sdc36c sdc36c di v p 10 downloaded from: http:///
max14820 io-link device transceiver 28 maxim integrated figure 15. using an optional external supply to power the max14820 figure 14. larger bypass capacitance for powering external circuits 1 2 4 3 10k max14820 0.8 1f 0.1f 1f v cc uv gpio2 ldoin do lxfb gnd spi in 5v step-down regulator en c/q l+ l- gnd di gnd v 5 v cc ldo33 v l txq microcontroller wu irq rx rx txc tx txen rts lo gpio1 3.3v max17501f 5v max14820 0.8 ? v cc ldoin l+ l- gnd v p v 5 ldo33 3.3v 5v 1f 0.1f 1f c5* c33* 10 ? * 10 ? * 10 ? 1f downloaded from: http:///
max14820 io-link device transceiver 29 maxim integrated ordering information + denotes a lead(pb)-free/rohs-compliant package. *ep = exposed pad. chip information process: bicmos package information for the latest package outline information and land patterns (foot - prints), go to www.maximintegrated.com/packages . note that a ?+?, ?#?, or ?-? in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. part temp range pin-package MAX14820ETG+ -40c to +85c 24 tqfn-ep* package type package code outline no. land pattern no. 24 tqfn-ep t2444+4 21-0139 90-0022 downloaded from: http:///
max14820 io-link device transceiver maxim integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim integrated product. no circuit patent licenses are implied. maxim integrated reserves the right to change the circuitry and specifications without notice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. maxim integrated 160 rio robles, san jose, ca 95134 usa 1-408-601-1000 30 ? 2014 maxim integrated products, inc. maxim integrated and the maxim integrated logo are trademarks of maxim integrated products, inc. revision history revision number revision date description pages changed 0 3/11 initial release ? 1 4/11 corrected do current level, corrected formatting and typos, added test condition to 2 typical operating characteristics graphs, and added information to pin description 1, 11, 13, 14, 15, 18, 23, 25, 27 2 6/11 changed di input threshold high and di input threshold low max ratings, changed v di specifications in table 2, changed pin description for i.c. pin 1, 4, 13, 17, 20 3 8/11 corrected c/q and do minimum and maximum ratings in the absolute maximum ratings section, corrected i cc maximum value and shuffled row parameters in the electrical characteristics table, replaced figures 10 and 11, added maxim part number for dc-dc regulator 3, 26 4 1/12 corrected typical operating circuit , iec number, short-circuit timing diagram , added new toc 17, and updated figure 11 1, 13, 26, 27, 28 5 7/12 updated formula in the thermal protection and considerations section, updated optional external powering section, and updated figure 14 18, 27, 28 6 3/14 corrected autoretry timingcorrected trademark added application information and application circuit for use of larger ldo bypass capacitors improved spi description in figures added need for rc network to ldoin for hot plug protection 1, 16-17, 26-28 downloaded from: http:///

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